DeepSeek, an emerging open-weight AI model, is a powerful example of this trend. Its development highlights the growing movement toward democratising AI, providing developers and enterprises with new ways to integrate intelligence across devices without the constraints of proprietary, cloud-based models.

With the latest release of DeepSeek-R1, this trend is accelerating. DeepSeek-R1 is trained via large-scale reinforcement learning from human feedback, allowing it to develop strong reasoning capabilities autonomously. Benchmark results show that it performs on par with OpenAI-o1-1217 on tasks like math, coding and factual knowledge retrieval. Moreover, DeepSeek-R1 includes distilled versions (1.5B, 7B, 14B, 32B, 70B) optimised for efficiency, making it highly relevant for edge computing.

But open-weight AI models alone aren’t enough. For AI at the edge to reach its full potential, it requires efficient, AI-native compute platforms that can handle these models in real-world scenarios. This is where innovations in low-power, high-performance MPUs and MCUs play a crucial role.

The AI compute challenge

AI workloads today are increasingly constrained by compute demands. The dominant model of AI deployment has been centred around large-scale cloud inference, where models like GPT-4 or Gemini require massive GPU clusters to function effectively. While this approach works for centralised applications, it becomes impractical for edge-based applications like smart cameras, industrial automation and intelligent IoT devices that need real-time processing and autonomy.

This challenge has driven demand for efficient AI models that can run closer to the data source, minimising latency, power consumption and connectivity dependencies, while also enhancing security and privacy. Open-weight models like DeepSeek-R1 are a step in the right direction, but they must be paired with the right AI-enabled silicon to unlock their true potential.

Why open-weight ai models matter

DeepSeek is part of a larger movement toward open AI innovation, following in the footsteps of models like LLaMA and Mistral. By offering transparency and flexibility through customisation, open-weight models enable developers to fine-tune AI for specialised applications (industrial IoT, automotive, robotics, etc.); reduce dependence on cloud providers for inference, lowering costs and increasing control; and optimise performance for edge deployments, where compute resources are constrained.

With DeepSeek-R1, this movement is evolving further. The distillation approach used in R1 allows for smaller, more efficient models that still retain high reasoning capabilities. This is critical for edge AI, where power and memory constraints make deploying large models infeasible.

AI at the edge

Open AI models like DeepSeek-R1 are just one part of the equation. To make AI truly viable at the edge, we need hardware designed to handle these models efficiently and cost-effectively.

At Synaptics, we’ve built the Astra platform with this exact challenge in mind. Astra is an AI-Native compute platform designed for power-efficient, multimodal AI inference in embedded and IoT devices. By leveraging Arm Cortex-A processors and tightly integrated AI acceleration, Astra enables real-time AI processing at the edge—without the need for cloud offloading.

The distilled models from DeepSeek-R1 provide an ideal complement to this approach. These models maintain high performance in reasoning tasks while significantly reducing compute requirements, making them well-suited for AI-native edge devices. This synergy between open AI models, distillation and optimised edge compute will define the next phase of AI innovation. Imagine a world where smart home devices can process user interactions locally, preserving privacy and reducing latency. Or where industrial sensors leverage AI for real-time anomaly detection, preventing costly downtime. Or, indeed, where AI-driven medical devices provide real-time diagnostics without requiring cloud connectivity. In these types of applications open-weight AI models with AI-native processors will redefine what’s possible.

Unlocking AI innovation

As AI adoption accelerates, the industry is recognising that proprietary, cloud-centric models alone won’t be enough. Open-weight AI like DeepSeek-R1 represents a pivotal shift toward scaleable, customisable and efficient intelligence, but to truly bring AI everywhere, we need compute platforms built for real-world constraints.

At Synaptics, we’re excited about this transformation. The combination of open AI models, distillation techniques and AI-native compute will shape the future of edge intelligence, empowering developers, businesses and industries to deploy AI in ways that were previously impossible.

By John Weil, Vice President of IoT and Edge AI Processor Business, Synaptics

Each channel isolated to 1000VDC making the new device a significant advancement in thermocouple technology. Offering unparalleled precision with an accuracy of ±0.5°C from 0 to 85°C and ±1°C from -40 to 125°C, the module delivers reliable performance in the most challenging environments.

The thermocouple module measures temperatures across an exceptional range from -200°C to +1,800°C at sampling rates of up to 40Hz per channel. This capability makes it ideal for applications ranging from cryogenic research to high-temperature industrial processes.

Each channel features galvanic isolation exceeding 1000VDC, enabling safe and accurate temperature measurement in high-voltage systems such as battery packs, power electronics, and electric vehicle components. This isolation eliminates current paths through thermocouple leads, ensuring reliable measurement accuracy by preventing ground loops and electrical interference that can compromise temperature readings.

“The combination of isolation, accuracy, and CAN bus integration makes it an ideal solution for applications where temperature monitoring is mission-critical,” said Joe Holdsworth, founder and CEO at Metis Engineering.

The device features comprehensive fault detection capabilities, including open-circuit and short-circuit detection that alerts users when thermocouple wires are broken, disconnected, or shorted to ground or power. This built-in diagnostic functionality ensures system reliability and reduces maintenance overhead.

Engineered for harsh industrial environments, the module with potted electronics features DIN rail mounting and IP67-rated JWPF connectors that enable daisy-chaining with additional modules for expanded measurement capabilities. The robust design supports input supply voltages from 9 to 32V, making it compatible with a wide range of industrial power systems.

The device ships with K-type miniature thermocouple connectors as standard, with support for multiple thermocouple types including K, J, T, N, S, E, B, and R configurations. This flexibility allows users to select the optimal thermocouple type for their specific application requirements.

The module’s configurable CAN bus speed and address, combined with the supplied DBC file, enables straightforward integration into existing CAN networks. This feature is particularly valuable for automotive applications and industrial automation systems where CAN bus communication is standard.

“The CAN bus integration reflects our commitment to providing sensors that integrate seamlessly into modern industrial and automotive systems,” added Holdsworth. “Engineers can quickly deploy multiple channels of high-precision temperature monitoring without complex integration challenges.”

https://metisengineering.com/product/8-channel-isolated-thermocouple/

https://metisengineering.com

“Making cellular IoT as simple and accessible as possible is a core mission at Nordic. By integrating the nuSIM standard into our nRF9151 and nRF9160 modules, we are removing the physical barrier to creating ultra-compact, robust, and cost-effective cellular IoT products. Developers can now manage connectivity entirely in the digital domain, from manufacturing to deployment. This is a significant step forward for the industry,” said Oyvind Birkenes, EVP Long-Range at Nordic Semiconductor.

nuSIM is an open standard approach to integrated SIM (iSIM) where SIM credentials are encrypted and managed within a secure, protected area of the device. By operating as a dedicated software component inside the secure Arm TrustZone of the nRF91 Series’ application processor, nuSIM removes all external SIM hardware, directly reducing the bill of materials (BOM) and saving valuable board space. This is ideal for cellular IoT devices deployed in harsh environments—for example in water metering or smart farming irrigation applications—as removing the SIM socket eliminates a common point of mechanical failure and protects against corrosion and vibration. The fully digital provisioning process streamlines the supply chain, allowing SIM profiles to be securely delivered to devices during manufacturing, simplifying logistics and reducing operational costs.

“While Nordic’s nRF91 Series is already the most power-optimized and highly integrated cellular IoT module series on the market, nuSIM is another way we can enhance the field life of our customers’ end products that may be expected to last years without battery replacement,” said Birkenes.

Integrating nuSIM on an nRF91 Series module is a one-time software integration process using Nordic’s powerful nRF Connect SDK (Software Development Kit) together with the Redtea Mobile nuSIM integration library, the code to integrate the nuSIM operating system in accordance with the open nuSIM specification. Once the nuSIM integration library is included in the device firmware, the factory provisioning workflow is straightforward.

After the application firmware containing the nuSIM is loaded onto an nRF91 Series module, a specialized software tool made by Redtea prepares the device to securely receive its SIM profile, then the tool connects to a selected network operator to securely download and install a unique SIM profile onto each device. The nuSIM implementation on the nRF91 Series has been security-evaluated and certified by the independent testing institute TÜV Nord in Germany, ensuring it meets the highest standards for security and reliability.

The nuSIM solution for the nRF91 Series is available now. The first mobile network operator (MNO) providing commercial profiles for nuSIM is Deutsche Telekoms, with more to follow. To access detailed documentation, software, and the necessary tools for development, Nordic customers and developers can see here.

www.nordicsemi.com

“With the launch of the MXO 3, we are bringing the breakthrough capabilities of our MXO technology to a more accessible, smaller
instrument class. This compact oscilloscope delivers the same cutting-edge performance and usability that our customers have come to expect, while opening up new possibilities for engineers at a variety of price points, especially with the addition of an eight-channel model – the only instrument of its kind in this class. At Rohde & Schwarz, we are committed to making advanced test and measurement tools available to more users, and our fast, precise and compact MXO 3 is another step forward in that mission,” said Philip Diegmann, Vice President of Oscilloscopes at Rohde & Schwarz.

The MXO 3 comes with four- and eight channels, and delivers fast and precise advanced MXO technology – previously available only in larger, higher-priced models – at lower price. The oscilloscope allows engineers to see more of their device under test’s signal than any other instrument in this class; users can instantly see more signal details and rare events.

Like other MXO models, the MXO 3 oscilloscopes are built around the MXO-EP processing ASIC technology developed by Rohde & Schwarz to deliver 4.5 million acquisitions per second, 600,000 trigger events per second with zone triggering (for isolating events in the time domain, including math and frequency domain signals), 50,000 FFTs per second for a more comprehensive analysis for applications like EMI and harmonic testing, 600,000 math operations per second, and more.

The MXO 3 models ensure accurate measurement isolation and results users can trust, including 12-bit vertical resolution in hardware at all sample rates allows users to observe small signal changes even of larger signals. An HD mode enhances signal details that would otherwise be buried in noise. It offers both noise reduction and up to 18 bits of vertical resolution – the highest in the industry. The HD mode operates at full sample rate and is implemented in hardware, ensuring precision without sacrificing speed.

The instrument has a 11.6” full-HD capacitive touchscreen, and weighs only 4kg. At 5U of rack height, it ensures efficient use of limited space in labs or testing environments.

The MXO 3 series oscilloscopes are available in both four- and eight-channel models, with bandwidth options including 100 MHz, 200 MHz, 350 MHz, 500 MHz, and 1 GHz. The starting price for the eight channel models sets another industry benchmark for affordability at just EUR 12,500 while the four-channel models start at EUR 5,350.

For users that need additional requirements, there is a variety of upgrades, including 16 integrated digital channels with a mixed signal oscilloscope (MSO) option, a 50MHz arbitrary waveform generator, protocol decoding and triggering options for numerous industry standard buses and a frequency response analyzer to expand the instrument’s capabilities.

https://www.rohde-schwarz.com/product/MXO3

www.rohde-schwarz.com

These are industry’s first PCIe Gen 6 switches manufactured using a 3nm process. The family is designed to deliver lower power consumption and support up to 160 lanes for high-density AI system connectivity. Advanced security features include a hardware root of trust and secure boot, utilizing post-quantum safe cryptography compliant with the Commercial National Security Algorithm Suite (CNSA) 2.0.

“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organised as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data centre solutions business unit.

Previous PCIe generations created bandwidth bottlenecks as data transferred between CPUs, GPUs, memory and storage, leading to underutilisation and wasted compute cycles. PCIe 6.0 doubles the bandwidth of PCIe 5.0 to 64 GT/s (giga transfers per second) per lane, providing the necessary data pipeline to keep the most powerful AI accelerators consistently supplied. Switchtec Gen 6 PCIe switches enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators and storage devices, and are designed to help data center architects scale to the potential of next generation AI and cloud infrastructure.

“By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy efficient switch we’ve ever produced,” said McCarson.

By acting as a high-performance interconnect, the switches allow for simpler, more direct interfaces between GPUs in a server rack, which is crucial for reducing signal loss and maintaining the low latency required by AI fabrics. The PCIe 6.0 standard also introduces Flow Control Unit (FLIT) mode, a lightweight Forward Error Correction (FEC) system and dynamic resource allocation.

These changes make data transfer more efficient and reliable, especially for small packets which are common in AI workloads. These updates lead to higher overall throughput and lower effective latency.

Switchtec Gen 6 PCIe switches feature 20 ports and 10 stacks with each port featuring hot- and surprise-plug controllers. Switchtec also supports NTB (Non-Transparent Bridging) to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain. The switches are designed with advanced error containment and comprehensive diagnostics and debug capabilities, a wide breadth of I/O interfaces and an integrated MIPS processor with bifurcation options at x8 and x16. Input and output reference clocks are based on PCIe stacks with four input clocks per stack. Visit the website to learn more about Microchip’s full portfolio of PCIe switches.

The Switchtec Gen 6 PCIe Switch family is supported by Microchip’s ChipLink diagnostic tools, offering comprehensive debug, diagnostics, configuration and analysis through an intuitive graphical user interface (GUI). ChipLink connects via in-band PCIe or sideband signals such as UART, TWI and EJTAG, enabling flexible, efficient monitoring and troubleshooting throughout design and deployment. The switches are also supported by the PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit with multiple interfaces.

www.microchip.com

“ADI Power Studio is more than a set of tools — it’s a design ecosystem,” said Robert Reay, Vice President and Fellow, Power Products, ADI. “By integrating new system-level and IC-level design capabilities into a single product family, we’re enabling engineers to streamline power management design and optimisation so they have the potential to get solutions to their customers faster.”

Today’s electronic systems require more power density than ever, with dozens or even hundreds of power rails and interdependent voltage domains. That complexity creates bottlenecks and requires rework during architecture decisions, component selection and validation. Power Studio addresses these challenges by providing a unified, intuitive workflow that helps engineering teams make better decisions earlier by simulating real-world performance with accurate models and automating key outputs, such as bill of materials and report generation. Together, the family of tools can facilitate shorter development cycles, reduce rework and increase speed at which engineers bring power-dense systems to market.

Power Studio Planner and Power Studio Designer are available now as part of the ADI Power Studio. These tools represent the first phase of ADI’s vision to deliver a fully connected power design workflow for customers, with ongoing updates and product announcements planned in the months ahead.

www.analog.com.

The Pi Vision 10.1 CM5 brings the power and flexibility of the Raspberry Pi Compute Module 5 to an industrial-grade, fully enclosed HMI platform. Designed for developers, makers and OEMs ready to move from prototyping to professional deployment, it delivers the full Raspberry Pi experience — now in a rugged, production-ready form.

Built from a solid aluminium structure and featuring a 10.1-inch multi-touch display with IP66 front protection, the Pi Vision 10.1 CM5 is engineered for durability in demanding environments. Every component, from the panel-mount enclosure to the high-brightness display, has been designed for continuous industrial operation.

With native compatibility with Raspberry Pi OS and full support for Clea OS, SECO’s Yocto-based secure operating system, developers can choose between rapid prototyping on Raspberry Pi OS and enterprise-grade management with Clea OS. This flexibility makes Pi Vision 10.1 CM5 the perfect bridge between the Raspberry Pi community and industrial-scale applications.

Running Clea OS, SECO’s Yocto-based operating system, Pi Vision 10.1 CM5 provides secure fleet management, real-time data processing, and AI-at-the-edge capabilities. Clea OS enables enterprises to manage connected devices, deploy and update applications seamlessly, and provides developers with an open, ready-to-use environment to accelerate innovation.

By combining the Raspberry Pi ecosystem with SECO’s industrial reliability, the Pi Vision 10.1 CM5 enables rapid development of intelligent HMI solutions with long-term durability and broad software compatibility. Its flexibility makes it ideal for a wide range of applications, including smart building and HVAC, industrial and factory control, retail and kiosk, vending and smart appliances.

The Pi Vision 10.1 CM5 is available in two configurations — 2 GB RAM / 16 GB eMMC and 8 GB RAM / 64 GB eMMC — both included in the limited launch offer.

Early access registration is now open to secure priority availability of the first production units and the exclusive launch price: SECO: Pi Vision 10.1 CM5

www.seco.com

Among the key enhancements are:

PulsonixSim – Fully Integrated ngspice-based Simulator
Pulsonix 14 introduces PulsonixSim, the new simulation option is built on the ngspice engine and tightly integrated into the Pulsonix schematic environment. It allows designers to attach models, place stimuli and run mixed-mode SPICE analysis, including transient, AC, DC, Monte Carlo, noise, transfer functions, and more – all without leaving the design environment and utilising the same library used for design and PCB layout. Simulation results can be plotted to full screen graph windows or local ‘in-design’ graphs.

3D Flexi Bend & Clipping Plane Enhancements
A new “lift-off” state for Flexi bend regions allows the flexible portion of the board to originate inside existing boundaries rather than exiting the board edge. The bend region transforms adaptively based on bend-radius parameters.

Additionally, a 3D clipping plane feature lets users selectively hide parts of the design along X, Y or Z axes (and reverse clipping direction) to inspect internal layers or buried elements more effectively.

Interactive HTML BOM & Graphical Comparison Tools
Pulsonix 14.0 supports the Interactive HTML BOM option that exports design and BOM data into a searchable, browser-friendly HTML format.

The Symbol / Footprint Compare and Design Revision Analyser tools highlight differences between design versions or symbols, either in dialog view or using overlaid graphics with dimming/lowlighting.

Usability Upgrades & Window Workflow
The user interface sees multiple enhancements: tear-off windows, dock bars, “find in dialog grids,” and faster category switching to streamline navigation and reduce friction when working with large designs or complex dialogs.

Circular Hatching Style
Pulsonix 14 adds a circular hatching style alongside traditional linear hatching. Circular hatching reduces sharp corner effects during etching, which helps minimise impedance variation for tracks adjacent to hatched copper zones

Major Update to Scripting and Automation
Version 14.0 replaces the legacy ActiveX automation system with a completely re-engineered, modern scripting framework developed in-house by Pulsonix. The new scripting environment provides greater flexibility, improved security, faster execution, and direct access to more Pulsonix objects and functions. Users can now automate complex design operations, customise workflows, and build bespoke productivity tools using industry-standard scripting languages.

Vault Integration & Version Control Enhancements
Vault improvements in Version 14 include visual thumbnail previews of items, “synchronise selected items” folder path alignment, definable permissions, Spice Model and Formal files in Vault and type-specific revision naming schemes – helping design teams maintain data integrity and traceability.

Pulsonix Version 14.0 is available now. Learn more about the new features and enhancements, by visiting www.pulsonix.com/latestversion

“Each year, our Halloween competition highlights the ingenuity of the Element14 Community. It is an opportunity for makers and engineers to share ideas, learn from one another, and celebrate their passion for electronics in a unique and engaging way,” said ,” Andreea Teodorescu, Global Director of Product Marketing & Element14 community.

This year’s challenge encourages participants to design and build projects that capture the spirit of Halloween using electronic components. Example submissions could include electronic decorations, zombie defences, automatic spooking machines, or wearable electronic costumes and props.

The competition will award prizes across multiple categories, including one first-place winner, three second-place winners, and three runner-up winners. Each winning participant will be able to select from a set of prizes.

To qualify, participants must submit a project write-up detailing their design and build process by 9 November 2025. Submissions should be made directly on the official competition page.

The competition is open to both new and long-standing community members, with a focus on creativity, effort, and knowledge-sharing.

For full details and to enter the competition, visit: https://community.element14.com/challenges-projects/halloween/b/news/posts/join-the-element14-community-2025-halloween-competition.

“Our long-term commitment to supporting the SPC58 family for automotive customers globally lets system designers confidently start new projects and continue to leverage their investments in device validations, software, and tooling,” said Luca Rodeschini, Group Vice President and General Purpose and Automotive Microcontrollers Division General Manager, STMicroelectronics. “The MCUs enable a flexible, platform-based approach and future-proof scalability, presenting a broad selection of device variants that support evolving automotive electrical architectures.”

The complete portfolio comprises five general-purpose lines that are featured for smart gateways and body applications such as lighting and door locking, with communication, analogue and security peripherals. The high-performance SPC58 E and SPC58 N lines are also available and target powertrain-electrification and chassis-safety use cases. These provide additional special features including multiple types of timers and FlexPWM to address complex motor-control challenges.

Customers can now extend the lifetime of their successful products and continue to count on SPC58 automotive microcontrollers for new designs. The Company’s in-house manufacturing model ensures control over all aspects of device design, support, and production at its own semiconductor fabrication plants. ST similarly extended its longevity commitment to the SPC56 family of general-purpose and performance automotive microcontrollers in 2021.

Comprising seven product lines, the SPC58 family delivers:

• MCUs with up to three e200z4 32-bit Power Architecture cores and from 1MB to 10MB on-chip NVM, manufactured on ST’s 40nm embedded flash process.
• Extensive support for popular communication protocols including multiple ISO CAN-FD compliant modular controller area network (MCAN) modules that support multi-drop connectivity.
• An IEEE 802.3 10/100 Ethernet controller that supports IEEE 802.1Q virtual LAN to facilitate traffic management and segmentation.
• Hardware security module (HSM) with independent core and memory to isolate security-sensitive processes and data, enabling users to build EVITA^®-compliant systems. Hardware-based mechanisms that facilitate system functional-safety certification up to ISO 26262 ASIL-B.
• Devices in the high-performance SPC58 E and SPC58 N lines are featured for systems targeting ASIL-D, the highest specified safety-integrity level.

The SPC58 family comprises over 40 variants, from SPC58 2B devices in the economical and compact 10mm x 10mm eTQFP64 to SPC58 H MCUs in 19mm x 19mm FPBGA386. Local ST sales offices can provide pricing options and sample requests.

For more information, please go to SPC5 32-bit automotive MCUs

However, while the ISA itself is royalty-free, its implementations are not free from legal risks. The architecture may be open, but it exists within a patent-heavy environment, presenting increasing challenges for developers and startups. Many developers are pushing ahead with innovative designs, unaware of the intellectual property complexities that accompany hardware development. If left unaddressed, it could threaten the very openness this movement champions.

As most mainstream chip standards and architectures are predominantly controlled by major commercial entities such as Intel, AMD and ARM, access to high-performance semiconductor designs has increasingly become a matter of strategic concern. Export controls now restrict the sale of advanced chip technologies to China and other countries, aiming to limit their ability to produce cutting-edge semiconductors. In this context, RISC-V has emerged as a particularly attractive alternative, especially for China’s defence and research sectors, because it offers a geopolitically neutral, open-source architecture. According to the Shanghai Science and Technology Commission, RISC-V’s openness makes it a strategic choice for building domestic chip capabilities. A 2023 report by The Japan Times revealed that, in response to US sanctions, Chinese defence contractors, state-backed entities and academic institutions invested more than 50 million dollars in RISC-V projects between 2018 and 2023. Today, RISC-V chips are already being used in applications ranging from self-driving cars to artificial intelligence, showing how rapidly the technology is transitioning from research to real-world deployment.

The patent problem

RISC-V’s flexibility is both its greatest strength and its main legal vulnerability. The ISA promotes innovation where designers can customise various aspects of computer architecture, such as memory models, cache coherency, neuro technology, and hardware accelerators to fit their specific needs. However, these areas are also where patent risks frequently arise. Many modern SoCs include features such as hybrid branch predictors, boot-time power gating, and custom interrupt schedulers, which are components that may already be covered by patents held by companies such as Intel, IBM, Qualcomm, or ARM. The issue is: even if an engineer creates their bespoke implementation, they might still unintentionally infringe a patent. In patent law, originality does not shield you from legal action.

Patent filings related to RISC-V have surged in recent years. According to publications from The Japan Times, in China, RISC-V patent publications increased from around 10 in 2018 to approximately 1,061 in 2022, while US filings grew from about 10 to around 2,018 during the same period; see Figure 2. Similarly, Chinese fabless companies account for about 40% of global RISC-V patents, according to industry trackers. Worldwide, filings involving RISC-V have risen by more than 400% between 2018 and 2023, reflecting growing innovation, as well as increased competition and legal risks. Companies such as SiFive, Andes Technology, and Alibaba’s T‑Head are driving these trends, securing patents on microarchitecture innovations like vector units, custom accelerators, and cache management systems. Academic institutions are also entering the IP game, compounding the ecosystem’s legal complexity.

In the GCC, particularly, United Arab Emirates, RISC-V research and chip design are gaining momentum. The Technology Innovation Institute (TII) in Abu Dhabi has played a central role by joining RISC-V International in 2021. Additionally, the Neuromorphic Engineering Lab at the American University of Ras Al Khaimah is pioneering open-source chip design research in the northern emirate. In a notable first for the UAE, the research team successfully taped out an open-source healthcare platform using Google’s SkyWater 130nm process, setting a foundational step for domestic innovation.

Saudi Arabia, meanwhile, is laying the groundwork for a national semiconductor ecosystem that may soon embrace RISC-V. As reported by Arab News in 2024, the Saudi government launched the National Semiconductor Hub (NSH) with a strategic funding commitment of $266m, aiming to incubate 50 fabless chip companies by 2030. While current investments are broad-based and not RISC-V specific, the infrastructure and funding environment are well-positioned to support open-source architectures in future Saudi chip initiatives.

As reviewed by Reuters, the number of RISC-V patents filed during 2018 – 2022 has grown significantly, primarily dominated by the US and China.

The open nature of RISC-V can sometimes gives the wrong impression that “open” automatically means “safe”. But that is not the case. Developers, especially those in universities or startups, need to understand that while the instruction set is free to use, the specific designs built on top of it can still run into patent issues. As RISC-V moves from the lab into commercial products, this misunderstanding can become a serious risk.

Startups are particularly vulnerable. They tend to focus on performance, power efficiency and chip size, but often do not have the legal resources to fully check for intellectual property problems. A clever new memory controller or accelerator can quickly become a liability if it overlaps with an existing patent. That could mean a costly redesign, licensing fees, production delays, or even losing investor confidence. A notable example is the Apple versus Rivos case (2022–2023), which highlighted how even open-source hardware projects can become entangled in serious legal disputes over intellectual property.

Making openness sustainable

For RISC-V to deliver on its promise, the community must evolve, not just technically, but legally. Developers need to treat intellectual property with the same rigour as performance or power efficiency. That means evaluating the originality of designs, considering potential patent overlaps, and building innovations defensibly. There are promising signs of progress. In 2023, nine major Chinese chipmakers, including Alibaba’s T‑Head, StarFive, and VeriSilicon, formed a patent‑sharing alliance, agreeing not to sue one another over RISC-V implementations. This model of cross-licensing offers a path for reducing litigation risk and fostering collaboration.

To extend this model globally, the RISC-V community can form a global patent pool where companies share key patents under fair, low-cost, or royalty-free terms, providing legal clarity for startups and open‑source developers. Another suggestion could be to create a certification scheme for “IP‑safe” RISC-V cores, offering assurance to downstream users and strengthening the ecosystem.

Going forward, RISC-V is one of the most exciting shifts in computing architecture in decades. It provides a democratised route to processor design, challenges the ARM–x86 duopoly, and drives global innovation forward. However, openness alone is not sufficient. To ensure it creates genuine opportunities rather than recreating old barriers, RISC-V must combine technical excellence with legal strategy, shared governance and community accountability. Only then can openness genuinely translate into opportunity and long-term progress.

By Arfan Ghani, Professor of Computer Engineering at the American University of Ras Al Khaimah, and Director, Neuromorphic Engineering Lab, United Arab Emirates

“We are excited to elevate the performance of embedded systems in the aerospace and defense industry with our new 3U VPX cards, combined with the latest AMD x86 embedded processor and RF and adaptive computing technologies,” said Craig Petrie, vice president, BittWare. “The opportunity to leverage BittWare’s proven design expertise along with AMD technology leadership will prove invaluable in giving customers more complete, interoperable solutions to meet ever-increasing demands for compact, rugged designs and highly reliable performance.”

The new BittWare 3U VPX cards leverage next-generation AMD Ryzen Embedded processors and AMD Versal RF Series devices, along with AMD Versal Series Gen 2 adaptive SoCs to yield a technological leap forward in data acquisition and multi-sensor processing. As a result, these cards will be especially useful for multi-channel, real-time data processing for radar, sensor fusion, electronic warfare, signals intelligence (SIGINT), unmanned aerial vehicles (UAVs) and image processing.

“Our ongoing collaboration with BittWare showcases how delivering integrated system-level solutions that combine AMD compute innovation with BittWare’s expertise in deployable x86 card-level solutions, helps to accelerate the adoption of AMD Versal adaptive SoCs and Ryzen Embedded x86 CPUs in defense applications,” said Minal Sawant, senior director, Aerospace and Defense Vertical Market, AMD. “Complementing AMD Versal adaptive devices, Ryzen Embedded processors are ideal for second-stage computing in advanced defense systems, combining software programmable x86 cores, integrated GPUs, and ML-capable NPUs. Rapid enablement of 3U VPX SOSA-aligned cards helps defense customers accelerate new designs for use in tomorrow’s most advanced radar, radio, sensor processing and mission computing systems.”

BittWare is extending its legacy of developing high-performance COTS products with the 3U VPX cards, including both SOSA (Sensor Open Systems Architecture) and VITA 48, which defines the mechanical requirements for building and cooling ruggedized electronic modules for embedded systems.

Users of VPX solutions are invited to apply for early access to BittWare’s new 3U VPX cards in advance of general availability to receive exclusive technical product details, roadmap information and opportunities to engage with experts on next-generation product designs.