DeepSeek, an emerging open-weight AI model, is a powerful example of this trend. Its development highlights the growing movement toward democratising AI, providing developers and enterprises with new ways to integrate intelligence across devices without the constraints of proprietary, cloud-based models.

With the latest release of DeepSeek-R1, this trend is accelerating. DeepSeek-R1 is trained via large-scale reinforcement learning from human feedback, allowing it to develop strong reasoning capabilities autonomously. Benchmark results show that it performs on par with OpenAI-o1-1217 on tasks like math, coding and factual knowledge retrieval. Moreover, DeepSeek-R1 includes distilled versions (1.5B, 7B, 14B, 32B, 70B) optimised for efficiency, making it highly relevant for edge computing.

But open-weight AI models alone aren’t enough. For AI at the edge to reach its full potential, it requires efficient, AI-native compute platforms that can handle these models in real-world scenarios. This is where innovations in low-power, high-performance MPUs and MCUs play a crucial role.

The AI compute challenge

AI workloads today are increasingly constrained by compute demands. The dominant model of AI deployment has been centred around large-scale cloud inference, where models like GPT-4 or Gemini require massive GPU clusters to function effectively. While this approach works for centralised applications, it becomes impractical for edge-based applications like smart cameras, industrial automation and intelligent IoT devices that need real-time processing and autonomy.

This challenge has driven demand for efficient AI models that can run closer to the data source, minimising latency, power consumption and connectivity dependencies, while also enhancing security and privacy. Open-weight models like DeepSeek-R1 are a step in the right direction, but they must be paired with the right AI-enabled silicon to unlock their true potential.

Why open-weight ai models matter

DeepSeek is part of a larger movement toward open AI innovation, following in the footsteps of models like LLaMA and Mistral. By offering transparency and flexibility through customisation, open-weight models enable developers to fine-tune AI for specialised applications (industrial IoT, automotive, robotics, etc.); reduce dependence on cloud providers for inference, lowering costs and increasing control; and optimise performance for edge deployments, where compute resources are constrained.

With DeepSeek-R1, this movement is evolving further. The distillation approach used in R1 allows for smaller, more efficient models that still retain high reasoning capabilities. This is critical for edge AI, where power and memory constraints make deploying large models infeasible.

AI at the edge

Open AI models like DeepSeek-R1 are just one part of the equation. To make AI truly viable at the edge, we need hardware designed to handle these models efficiently and cost-effectively.

At Synaptics, we’ve built the Astra platform with this exact challenge in mind. Astra is an AI-Native compute platform designed for power-efficient, multimodal AI inference in embedded and IoT devices. By leveraging Arm Cortex-A processors and tightly integrated AI acceleration, Astra enables real-time AI processing at the edge—without the need for cloud offloading.

The distilled models from DeepSeek-R1 provide an ideal complement to this approach. These models maintain high performance in reasoning tasks while significantly reducing compute requirements, making them well-suited for AI-native edge devices. This synergy between open AI models, distillation and optimised edge compute will define the next phase of AI innovation. Imagine a world where smart home devices can process user interactions locally, preserving privacy and reducing latency. Or where industrial sensors leverage AI for real-time anomaly detection, preventing costly downtime. Or, indeed, where AI-driven medical devices provide real-time diagnostics without requiring cloud connectivity. In these types of applications open-weight AI models with AI-native processors will redefine what’s possible.

Unlocking AI innovation

As AI adoption accelerates, the industry is recognising that proprietary, cloud-centric models alone won’t be enough. Open-weight AI like DeepSeek-R1 represents a pivotal shift toward scaleable, customisable and efficient intelligence, but to truly bring AI everywhere, we need compute platforms built for real-world constraints.

At Synaptics, we’re excited about this transformation. The combination of open AI models, distillation techniques and AI-native compute will shape the future of edge intelligence, empowering developers, businesses and industries to deploy AI in ways that were previously impossible.

By John Weil, Vice President of IoT and Edge AI Processor Business, Synaptics

These are industry’s first PCIe Gen 6 switches manufactured using a 3nm process. The family is designed to deliver lower power consumption and support up to 160 lanes for high-density AI system connectivity. Advanced security features include a hardware root of trust and secure boot, utilizing post-quantum safe cryptography compliant with the Commercial National Security Algorithm Suite (CNSA) 2.0.

“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organised as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data centre solutions business unit.

Previous PCIe generations created bandwidth bottlenecks as data transferred between CPUs, GPUs, memory and storage, leading to underutilisation and wasted compute cycles. PCIe 6.0 doubles the bandwidth of PCIe 5.0 to 64 GT/s (giga transfers per second) per lane, providing the necessary data pipeline to keep the most powerful AI accelerators consistently supplied. Switchtec Gen 6 PCIe switches enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators and storage devices, and are designed to help data center architects scale to the potential of next generation AI and cloud infrastructure.

“By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy efficient switch we’ve ever produced,” said McCarson.

By acting as a high-performance interconnect, the switches allow for simpler, more direct interfaces between GPUs in a server rack, which is crucial for reducing signal loss and maintaining the low latency required by AI fabrics. The PCIe 6.0 standard also introduces Flow Control Unit (FLIT) mode, a lightweight Forward Error Correction (FEC) system and dynamic resource allocation.

These changes make data transfer more efficient and reliable, especially for small packets which are common in AI workloads. These updates lead to higher overall throughput and lower effective latency.

Switchtec Gen 6 PCIe switches feature 20 ports and 10 stacks with each port featuring hot- and surprise-plug controllers. Switchtec also supports NTB (Non-Transparent Bridging) to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain. The switches are designed with advanced error containment and comprehensive diagnostics and debug capabilities, a wide breadth of I/O interfaces and an integrated MIPS processor with bifurcation options at x8 and x16. Input and output reference clocks are based on PCIe stacks with four input clocks per stack. Visit the website to learn more about Microchip’s full portfolio of PCIe switches.

The Switchtec Gen 6 PCIe Switch family is supported by Microchip’s ChipLink diagnostic tools, offering comprehensive debug, diagnostics, configuration and analysis through an intuitive graphical user interface (GUI). ChipLink connects via in-band PCIe or sideband signals such as UART, TWI and EJTAG, enabling flexible, efficient monitoring and troubleshooting throughout design and deployment. The switches are also supported by the PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit with multiple interfaces.

www.microchip.com

“Enclustra is committed to pushing the boundaries of FPGA and SoM innovation. This launch strengthens our ability to deliver Edge AI solutions that empower industries to scale AI adoption efficiently,” said Philipp Baechtold, CEO of Enclustra.

The Modalix SoM provides a high-performance, energy-efficient solution that enables organisations in manufacturing, robotics, industrial automation, aerospace, and defence to integrate advanced AI capabilities faster, more reliably, and at scale.

Its benefits include seamless integration and flexibility – compact design with extensive I/O options ensures compatibility with GPU-based SoMs and existing architectures; the SiMa.ai’s ONE platform for Physical AI, including the Palette and Palette Edgematic software suites, streamlines development with Python, PyTorch, and OpenCV; and advanced thermal management and performance monitoring ensure dependable operation across industries with demanding requirements.

“The introduction of our Modalix SoM represents a critical expansion into Physical AI, addressing the diverse needs of robotics, automation, and autonomous systems. Together with Enclustra, we are removing integration barriers and making it remarkably simple for companies worldwide to upgrade from legacy systems to Modalix’s superior performance,” said Krishna Rangasayee, CEO and Founder of SiMa.ai.

Engineering samples of the MLSoC Modalix SoM are available now through Enclustra’s exclusive Early Access Program. Customers can order today.

www.enclustra.com

“As a result of close collaboration on development and integration with Tobii, we have created a new generation of interior sensing technology that is reliable, user-friendly, and ready for widespread adoption across the automotive industry,” said Alexandre Balmefrezol, Executive Vice President and General Manager of the Imaging Sub-Group at STMicroelectronics.

Tobii’s and ST’s integrated approach allows automotive OEMs to install just one camera inside the cabin, providing the most mature, efficient, and cost-effective solution available on the market.

The system combines Tobii’s attention-computing technology with STMicroelectronics’s VD1940, an advanced image sensor designed primarily for automotive applications. This sensor features a single 5.1MP hybrid pixel design, sensitive to both RGB (color in daytime) and infrared (IR at nighttime) light. Its wide-angle field of view covers the entire cabin, delivering exceptional image quality. Tobii’s algorithms process dual video streams to support both the Driver Monitoring System (DMS) and Occupancy Monitoring System (OMS).

“Image quality is critical, and thanks to our strong collaboration with ST, we’ve achieved a unique balance that allows a single-camera solution to meet rigorous safety standards, while also unlocking enhanced user experiences. By combining visible and IR sensing, we’re enabling intelligent in-cabin environments that truly understand human presence, behaviour, and context,” said said Adrian Capata, senior vice president of Tobii Autosense.

The VD1940 image sensor is part of the SafeSense by ST, an advanced sensing technology platform designed by STMicroelectronics for DMS and OMS. which embeds functional safety and cyber security features and is dedicated to automotive safety applications. With this innovative product portfolio ST is delivering reliable, high-quality, and cost-effective solutions tailored to the automotive industry. As an Integrated Device Manufacturer (IDM), STMicroelectronics masters the complete image sensor supply chain, with full control over both design and manufacturing processes. This ensures supply security through production of its imaging solutions in its European fabs, with these devices already in mass production and ready for integration by Tier 1s and OEMs.

www.tobii.com

www.st.com

“In an era of geopolitical uncertainty, with cybersecurity issues and armed conflicts on the rise, Europe’s technological sovereignty is more and more inseparable from sovereign hardware, whether for civil applications or, more importantly, defence. It was therefore natural for SiPearl to capitalise on the expertise developed by its R&D teams in HPC to develop a new version of our first processor that perfectly meets the needs of dual-use purposes. As part of the roadmap entrusted to us by Europe to foster the return of high-performance processor technologies to the continent, Athena1 is the perfect complement to Rhea1 in helping to assert Europe’s strategic independence”, concluded Philippe Notton, CEO and founder of SiPearl.

Based on the unique expertise in Europe developed for the design of Rhea1 (SiPearl’s first generation processor, dedicated to HPC), Athena1 will offer features specifically tailored to the workloads of government, defence and aerospace applications. These include, for example, secure communications and intelligence, cryptography and encryption, intelligence processing, tactical networks, electronic detection or local data processing on vehicles.

In addition to its computing power, Athena1 will be characterised by its security and integrity. The Athena1 family will offer skus of 16, 32, 48, 64 or 80 Arm Neoverse V1 cores, depending on the power required for each application and their thermal constraints, among other factors. Detailed technical specifications will be announced at a later date.

The manufacturing of Athena1’s die will be entrusted to TSMC, the world’s leading independent foundry for advanced semiconductors. Packaging will initially be carried out in Taiwan, but packaging is targeted to be moved to Europe to help to grow this industrial ecosystem in Europe.

Athena1 will be commercially available in the second half of 2027.

]]> https://www.electronicsworld.co.uk/new-ai-native-processor-for-edge-applications-offers-100x-power-and-performance-improvements-over-32-bit-mcus/39626/ Wed, 17 Sep 2025 08:23:15 +0000 https://www.electronicsworld.co.uk/?p=39626 AI processor company, Ambient Scientific, launches the GPX10 Pro, a system-on-chip (SoC) which uses innovative AI-native silicon technology to enable high-performance AI inference on battery-powered edge devices. The AI engine supports important neural networking model types, including CNNs, RNNs, LSTMs and GRUs, at the edge.

Ambient Scientific provides the comprehensive Nebula AI enablement toolchain to accelerate the training, development and deployment of AI models to the GPX10 and GPX10 Pro. It is compatible with leading model training frameworks including TensorFlow, Keras and ONNX. The chip’s AI cores, which are programmable in the Nebula toolchain, give designers the flexibility to adapt to evolving AI model types and topologies.

“Chiplet integration is reshaping how the industry thinks about performance, scaleability and time to market,” said Robin Davis, VP of Strategic Engagements & Applications at Deca. “Our partnership with SST empowers customers to develop a chiplet solution that combines different chips, process nodes, sizes and even die from multiple foundries delivering more efficient and cost-effective products.”

Chiplet technology offers significant advantages in semiconductor design and manufacturing by enabling a more-than-Moore approach. Designers can go beyond traditional scaling to deliver enhanced functionality and performance and get products to market faster. Chiplets allow the reuse of existing IP and can facilitate the mixing of advanced process nodes with less expensive legacy geometries. By utilizing the most appropriate die technology for a particular function, chiplets provide a versatile, efficient and economical pathway for advanced semiconductor innovation.

“As our customers push the boundaries of Moore’s Law, they are expressing greater interest in chiplet-based solutions,” said Mark Reiten, Vice President of Microchip’s licensing business unit. “This partnership aims to deliver a comprehensive package of IP, simulation tools and advanced assembly and engineering services necessary for successful chiplet development and productization.”

This collaboration combines Deca’s M-Series fan-out and Adaptive Patterning technologies with SST’s industry-leading SuperFlash embedded flash technology. The companies are applying their system-level integration expertise to deliver a bundled offering that empowers customers to design, verify and commercialize NVM chiplets. By enabling greater architectural flexibility, the solution offers both technical and commercial advantages over traditional monolithic integration.

The collaborative solution provides a modular, memory-centric foundation for advanced multi-die architectures by combining the strengths of both companies. The chiplet package leverages SST’s SuperFlash technology, along with the interface logic and physical design elements required to function as a self-contained chiplet. This is paired with Adaptive Patterning-based redistribution layer (RDL) design rules, simulation flows, test strategies and manufacturing paths through Deca’s ecosystem of qualified partners.

Deca and SST will jointly support customers from early design through qualification and prototype manufacturing. By streamlining integration and accelerating design cycles, the companies aim to enable broader adoption of heterogeneous integration, engaging with customers globally to bring chiplet solutions to market.

SST website  Deca website

However, while the ISA itself is royalty-free, its implementations are not free from legal risks. The architecture may be open, but it exists within a patent-heavy environment, presenting increasing challenges for developers and startups. Many developers are pushing ahead with innovative designs, unaware of the intellectual property complexities that accompany hardware development. If left unaddressed, it could threaten the very openness this movement champions.

As most mainstream chip standards and architectures are predominantly controlled by major commercial entities such as Intel, AMD and ARM, access to high-performance semiconductor designs has increasingly become a matter of strategic concern. Export controls now restrict the sale of advanced chip technologies to China and other countries, aiming to limit their ability to produce cutting-edge semiconductors. In this context, RISC-V has emerged as a particularly attractive alternative, especially for China’s defence and research sectors, because it offers a geopolitically neutral, open-source architecture. According to the Shanghai Science and Technology Commission, RISC-V’s openness makes it a strategic choice for building domestic chip capabilities. A 2023 report by The Japan Times revealed that, in response to US sanctions, Chinese defence contractors, state-backed entities and academic institutions invested more than 50 million dollars in RISC-V projects between 2018 and 2023. Today, RISC-V chips are already being used in applications ranging from self-driving cars to artificial intelligence, showing how rapidly the technology is transitioning from research to real-world deployment.

The patent problem

RISC-V’s flexibility is both its greatest strength and its main legal vulnerability. The ISA promotes innovation where designers can customise various aspects of computer architecture, such as memory models, cache coherency, neuro technology, and hardware accelerators to fit their specific needs. However, these areas are also where patent risks frequently arise. Many modern SoCs include features such as hybrid branch predictors, boot-time power gating, and custom interrupt schedulers, which are components that may already be covered by patents held by companies such as Intel, IBM, Qualcomm, or ARM. The issue is: even if an engineer creates their bespoke implementation, they might still unintentionally infringe a patent. In patent law, originality does not shield you from legal action.

Patent filings related to RISC-V have surged in recent years. According to publications from The Japan Times, in China, RISC-V patent publications increased from around 10 in 2018 to approximately 1,061 in 2022, while US filings grew from about 10 to around 2,018 during the same period; see Figure 2. Similarly, Chinese fabless companies account for about 40% of global RISC-V patents, according to industry trackers. Worldwide, filings involving RISC-V have risen by more than 400% between 2018 and 2023, reflecting growing innovation, as well as increased competition and legal risks. Companies such as SiFive, Andes Technology, and Alibaba’s T‑Head are driving these trends, securing patents on microarchitecture innovations like vector units, custom accelerators, and cache management systems. Academic institutions are also entering the IP game, compounding the ecosystem’s legal complexity.

In the GCC, particularly, United Arab Emirates, RISC-V research and chip design are gaining momentum. The Technology Innovation Institute (TII) in Abu Dhabi has played a central role by joining RISC-V International in 2021. Additionally, the Neuromorphic Engineering Lab at the American University of Ras Al Khaimah is pioneering open-source chip design research in the northern emirate. In a notable first for the UAE, the research team successfully taped out an open-source healthcare platform using Google’s SkyWater 130nm process, setting a foundational step for domestic innovation.

Saudi Arabia, meanwhile, is laying the groundwork for a national semiconductor ecosystem that may soon embrace RISC-V. As reported by Arab News in 2024, the Saudi government launched the National Semiconductor Hub (NSH) with a strategic funding commitment of $266m, aiming to incubate 50 fabless chip companies by 2030. While current investments are broad-based and not RISC-V specific, the infrastructure and funding environment are well-positioned to support open-source architectures in future Saudi chip initiatives.

As reviewed by Reuters, the number of RISC-V patents filed during 2018 – 2022 has grown significantly, primarily dominated by the US and China.

The open nature of RISC-V can sometimes gives the wrong impression that “open” automatically means “safe”. But that is not the case. Developers, especially those in universities or startups, need to understand that while the instruction set is free to use, the specific designs built on top of it can still run into patent issues. As RISC-V moves from the lab into commercial products, this misunderstanding can become a serious risk.

Startups are particularly vulnerable. They tend to focus on performance, power efficiency and chip size, but often do not have the legal resources to fully check for intellectual property problems. A clever new memory controller or accelerator can quickly become a liability if it overlaps with an existing patent. That could mean a costly redesign, licensing fees, production delays, or even losing investor confidence. A notable example is the Apple versus Rivos case (2022–2023), which highlighted how even open-source hardware projects can become entangled in serious legal disputes over intellectual property.

Making openness sustainable

For RISC-V to deliver on its promise, the community must evolve, not just technically, but legally. Developers need to treat intellectual property with the same rigour as performance or power efficiency. That means evaluating the originality of designs, considering potential patent overlaps, and building innovations defensibly. There are promising signs of progress. In 2023, nine major Chinese chipmakers, including Alibaba’s T‑Head, StarFive, and VeriSilicon, formed a patent‑sharing alliance, agreeing not to sue one another over RISC-V implementations. This model of cross-licensing offers a path for reducing litigation risk and fostering collaboration.

To extend this model globally, the RISC-V community can form a global patent pool where companies share key patents under fair, low-cost, or royalty-free terms, providing legal clarity for startups and open‑source developers. Another suggestion could be to create a certification scheme for “IP‑safe” RISC-V cores, offering assurance to downstream users and strengthening the ecosystem.

Going forward, RISC-V is one of the most exciting shifts in computing architecture in decades. It provides a democratised route to processor design, challenges the ARM–x86 duopoly, and drives global innovation forward. However, openness alone is not sufficient. To ensure it creates genuine opportunities rather than recreating old barriers, RISC-V must combine technical excellence with legal strategy, shared governance and community accountability. Only then can openness genuinely translate into opportunity and long-term progress.

By Arfan Ghani, Professor of Computer Engineering at the American University of Ras Al Khaimah, and Director, Neuromorphic Engineering Lab, United Arab Emirates

By providing these powerful, pre-packaged solutions, SECO allows customers to dramatically reduce their time-to-market and focus their engineering resources on their final application and unique value proposition by abstracting the challenges of AI development. The newly available applications include:

• LLM – Local Chatbot with Intel OpenVINO: Using the efficient Phi model and optimised with OpenVINO, it enables offline conversational AI on the edge. This is ideal for creating interactive smart assistants, intelligent device manuals, and private-by-design customer service kiosks that do not rely on cloud connectivity.
• Speech-to-Text: Leveraging OpenAI’s powerful Whisper model on TensorFlow, this application delivers highly accurate voice transcription at the edge. It can be used to enable voice commands in HMIs, transcribe meetings in real-time, or create accessibility tools. An OpenVINO-compatible release is planned for the near future, promising enhanced performance on Intel architectures.
• Anti-Spoofing: A critical security enhancement for any device using facial recognition. This algorithm intelligently analyses a video stream from a standard RGB camera to distinguish between a live person and a static image or digital photo, preventing fraudulent access attempts via spoofing. This level of security is often mandatory in specific sectors such as the defence industry.
• Fitness Tracker – Time Series Classification: This algorithm interfaces with smart-bands or other wearables to process accelerometer and gyroscope data in real-time, providing the foundation for next-generation wellness and sports monitoring applications.
• Image Super Resolution: A sophisticated AI upscaling tool that intelligently enhances the resolution and quality of images and video frames. This has significant applications in medical imaging for clearer diagnoses, surveillance for identifying details, and in restoring legacy digital media.
• Image Analysis for Defect – Training Experience: An application designed to simplify the creation of quality control systems in manufacturing. It provides a streamlined experience for training a model to automatically detect production defects, improving quality and reducing operational costs.

“We’re progressively releasing more and more AI applications on the Application Hub, and they will be soon available for one-click deployment on the Clea Framework. Stay tuned for our upcoming monthly releases,” says Fausto Di Segni, Head of IoT and AI at SECO.

These new releases build on the App Hub’s foundational promise of vast hardware compatibility across leading vendors like Intel, Qualcomm, NXP, AMD, Rockchip, and MediaTek, all covered by SECO’s enterprise Long-Term Support on solutions featuring these chipsets, in addition to its upcoming turnkey deployment capability through the Clea Framework.

The new applications are now available for exploration on the SECO Application Hub.

With industry’s first 245.76TB NVMe SSD in a 2.5-inch and enterprise and datacenter standard form factor, KIOXIA’s LC9 series drives are well-suited to generative AI and enterprise applications.

“We recognise KIOXIA for its BiCS FLASH 3D flash memory and KIOXIA LC9 Series SSD. This solution enabled by their CMOS directly bonded to array (CBA) technology and the innovation of a 32-die stacked architecture in a package deliver the capacity, power and density required for transformational SSDs. Creating the highest capacity PCIe 5.0 enterprise SSD is a remarkable achievement,” said Jay Kramer, Chair of the Awards Program and President of Network Storage Advisors. “

The combination of advanced memory architecture and CBA technology enables 8TB in a small 154 BGA package – also an industry first. This milestone was made possible with advancements in KIOXIA’s high-precision wafer processing, material design, and wire bonding technologies.

KIOXIA LC9 Series SSDs are now sampling to customers.

www.kioxia.com

The new BSM technology provides a better solution to traditional sputtering and plating processes, addressing the reliability, warpage, and increasing thermal management challenges in hybrid bonding, wafer and Panel Level Packaging (PLP) metallization.

As AI chips and high-performance computing devices continue to push the limits of processing power, thermal density has risen significantly, making efficient heat dissipation more critical than ever. Reliable bonding between semiconductor packages and Thermal Interface Materials (TIM) is essential for effective heat transfer. However, conventional BSM methods—such as sputtering and plating—pose challenges related to cost, equipment requirements, scaling at larger panels, and environmental impact.

By leveraging Merck KGaA, Darmstadt, Germany’s expertise in semiconductor coating processes and Electroninks’s Metal-Organic Decomposition (MOD) Ink technology, this collaboration aims to redefine the standards for BSM in advanced semiconductor packaging.

Merck KGaA, Darmstadt, Germany and Electroninks remain committed to advancing their strategy and commercial offerings in advanced packaging. With the commercialization of this pioneering BSM technology, which is now underway at customer sites globally,  they aim to contribute to the advancement of high-efficiency, more sustainable semiconductor packaging solutions on silicon wafer, as well as panel level processing where limited solutions exist today.

The companies plan to develop and market this technology together to customers in the near future, with on-site technical support in the US and APAC.

Find out more at www.electroninks.com

The new SOP Advance(E) package marks a substantial improvement over Toshiba’s existing SOP Advance(N) package, reducing package resistance by approximately 65% and thermal resistance by approximately 15%. These package enhancements directly translate into superior device performance. The 80V TPM1R908QM exhibits a reduction in drain-source on-resistance (RDS(ON)) of approximately 21% and channel-case thermal resistance (Rth(ch-c)) of approximately 15% when compared to Toshiba’s existing product, the TPH2R408QM, of same voltage rating. Similarly, the 150V TPM7R10CQ5 achieves approximately 21% lower RDS(ON) and approximately 15% lower Rth(ch-ch) than Toshiba’s existing TPH9R00CQ5, also at the same voltage. The TPM7R10CQ5 is equipped with a high speed body diode for increased efficiency in synchronous rectification.

The reductions in on-resistance and suppressed temperature rise due to improved thermal resistance contribute to a lower overall on-resistance, even considering positive temperature characteristics. This combination ultimately achieves lower loss and higher efficiency in critical applications such as switched-mode power supplies for industrial equipment, including those powering data centres and communication base stations.

The TPM1R908QM features a drain-source voltage (VDSS) of 80V, a drain current (ID) of 238A (Tc=25°C), and a maximum RDS(ON) of 1.9mΩ (VGS=10V). The TPM7R10CQ5 offers a VDSS of 150V, an ID of 120A (Tc=25°C), and a maximum RDS(ON) of 7.1mΩ (VGS=10V). Both products have a channel temperature (Tch) of 175°C and a maximum Rth(ch-c) of 0.6°C/W (Tc=25°C). The SOP Advance(E) package typically measures 4.9mm × 6.1mm.

To further support circuit design for switched-mode power supplies, Toshiba also provides a G0 SPICE model for quick circuit function verification, alongside highly accurate G2 SPICE models that precisely reproduce transient characteristics.

Please follow the links for more information on the TPM1R908QM and TPM7R10CQ5.