“Our new image sensors with hybrid global and rolling shutter modes allow our customers to optimize image capture, ensuring motion-artifact-free video capture and low-noise, high-detail imaging at the same time, making it ideal for high-speed automated manufacturing processes and object tracking. This architecture is unique on market today and provides unmatched flexibility, performance, and integration. We continue to broaden our portfolio of solutions for a wide range of industrial applications and want to bring the best of optical sensing technologies to both existing and new applications,” said Alexandre Balmefrezol, Executive Vice President and General Manager of STMicroelectronics’s Imaging Sub-Group.

The VD1943, VD5943, VB1943, and VB5943 sensors, part of the ST BrightSense portfolio, are ready for evaluation and sampling, with mass production scheduled to begin in February 2026.

The RGB-IR variants of the sensors feature on-chip RGB-IR separation, eliminating the need for additional components and simplifying system design. This capability supports multiple output patterns, including 5MP RGB-NIR 4×4, 5MP RGB Bayer, 1.27MP NIR subsampling, and 5MP NIR smart upscale, with independent exposure times and instant output pattern switching. This integration reduces costs while maintaining full 5MP resolution for both color and infrared imaging.

The sensors incorporate backside illumination (BSI) and capacitive deep trench isolation (CDTI) pixel technologies to enhance sensitivity and sharpness, particularly in low lighting conditions. Single-frame on-chip HDR improves detail visibility across bright and dark areas. These features enable high-quality imaging in challenging environments and support advanced machine vision and edge AI applications.

Using 2.25 µm pixel technology and advanced 3D stacking, the sensors deliver high image quality in a smaller footprint. The die size is 5.76 mm by 4.46 mm, with a package size of 10.3 mm by 8.9 mm, and an industry-leading 73%-pixel array-to-die surface ratio. This compact design enables integration into space-constrained embedded vision systems without compromising performance.

“Industrial and security imaging are pushing sensor performance to new levels, enabling functions from identification to robotic guidance, gauging and advanced monitoring and inspection,” said Florian Domengie, PhD Principal Analyst Imaging at Yole Group. “By 2030, this image sensor market is projected to reach $3.9 billion with over 500 million units shipped. Key advances will include enhanced low-light performance, on-chip intelligence, and hybrid global/rolling shutter operation, combining low noise with high-precision temporal sensing.”

 www.st.com

Developed by ipTEST, Microtest’s UK subsidiary and a global leader in high-volume power semiconductor testing systems, the two platforms set a new benchmark in precision testing. They assess the ability of devices to handle high currents and voltages safely and efficiently.

Quasar²⁰⁰and Pulsar⁶⁰⁰ are designed for two key communities in the sector: academic researchers and engineers developing new semiconductor products. With a plug-and-play approach, they simplify experimental workflows by eliminating the need for custom equipment and reducing manual operations such as soldering and complex test setups. This enables users to obtain accurate, publication-ready results with traceable precision. Their reliability speeds up datasheet generation, facilitates correlation with production testers, and ensures safe validation of next-generation devices.

Quasar²⁰⁰ is suitable for evaluating Si (silicon), GaN (gallium nitride), and SiC (silicon carbide) devices. It delivers fast and accurate DC/AC measurements with minimal parasitic inductance. Its counterpart, Pulsar⁶⁰⁰, extends these capabilities to ultra-high current applications, ideal for testing SiC inverters and automotive systems, supporting short-circuit tests up to 1,000 A DC and 10,000 A+ AC.

Both platforms offer up to ±0.1% measurement accuracy across all voltage and current waveforms, with typical parasitic inductance below 30 nH in AC tests. UKAS (United Kingdom Accreditation Service)-traceable calibration and comprehensive audit logs ensure reliability, consistency, and compliance from lab benches to production lines.

From a safety perspective, ipTEST’s SocketSafe technology and a fully enclosed test environment with interlocked access protect both operators and hardware – crucial during high-stress or destructive testing. This safeguards investments, maximizes uptime, and ensures peace of mind when pushing devices to their performance limits.

Finally, low-inductance test sockets – connectors designed to minimize inductance and avoid interference with critical measurements – and a modular design make it easy to evaluate and configure both packaged and bare die samples, streamlining setup and reducing complexity.

www.microtest.net

These are industry’s first PCIe Gen 6 switches manufactured using a 3nm process. The family is designed to deliver lower power consumption and support up to 160 lanes for high-density AI system connectivity. Advanced security features include a hardware root of trust and secure boot, utilizing post-quantum safe cryptography compliant with the Commercial National Security Algorithm Suite (CNSA) 2.0.

“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organised as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data centre solutions business unit.

Previous PCIe generations created bandwidth bottlenecks as data transferred between CPUs, GPUs, memory and storage, leading to underutilisation and wasted compute cycles. PCIe 6.0 doubles the bandwidth of PCIe 5.0 to 64 GT/s (giga transfers per second) per lane, providing the necessary data pipeline to keep the most powerful AI accelerators consistently supplied. Switchtec Gen 6 PCIe switches enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators and storage devices, and are designed to help data center architects scale to the potential of next generation AI and cloud infrastructure.

“By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy efficient switch we’ve ever produced,” said McCarson.

By acting as a high-performance interconnect, the switches allow for simpler, more direct interfaces between GPUs in a server rack, which is crucial for reducing signal loss and maintaining the low latency required by AI fabrics. The PCIe 6.0 standard also introduces Flow Control Unit (FLIT) mode, a lightweight Forward Error Correction (FEC) system and dynamic resource allocation.

These changes make data transfer more efficient and reliable, especially for small packets which are common in AI workloads. These updates lead to higher overall throughput and lower effective latency.

Switchtec Gen 6 PCIe switches feature 20 ports and 10 stacks with each port featuring hot- and surprise-plug controllers. Switchtec also supports NTB (Non-Transparent Bridging) to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain. The switches are designed with advanced error containment and comprehensive diagnostics and debug capabilities, a wide breadth of I/O interfaces and an integrated MIPS processor with bifurcation options at x8 and x16. Input and output reference clocks are based on PCIe stacks with four input clocks per stack. Visit the website to learn more about Microchip’s full portfolio of PCIe switches.

The Switchtec Gen 6 PCIe Switch family is supported by Microchip’s ChipLink diagnostic tools, offering comprehensive debug, diagnostics, configuration and analysis through an intuitive graphical user interface (GUI). ChipLink connects via in-band PCIe or sideband signals such as UART, TWI and EJTAG, enabling flexible, efficient monitoring and troubleshooting throughout design and deployment. The switches are also supported by the PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit with multiple interfaces.

www.microchip.com

“Enclustra is committed to pushing the boundaries of FPGA and SoM innovation. This launch strengthens our ability to deliver Edge AI solutions that empower industries to scale AI adoption efficiently,” said Philipp Baechtold, CEO of Enclustra.

The Modalix SoM provides a high-performance, energy-efficient solution that enables organisations in manufacturing, robotics, industrial automation, aerospace, and defence to integrate advanced AI capabilities faster, more reliably, and at scale.

Its benefits include seamless integration and flexibility – compact design with extensive I/O options ensures compatibility with GPU-based SoMs and existing architectures; the SiMa.ai’s ONE platform for Physical AI, including the Palette and Palette Edgematic software suites, streamlines development with Python, PyTorch, and OpenCV; and advanced thermal management and performance monitoring ensure dependable operation across industries with demanding requirements.

“The introduction of our Modalix SoM represents a critical expansion into Physical AI, addressing the diverse needs of robotics, automation, and autonomous systems. Together with Enclustra, we are removing integration barriers and making it remarkably simple for companies worldwide to upgrade from legacy systems to Modalix’s superior performance,” said Krishna Rangasayee, CEO and Founder of SiMa.ai.

Engineering samples of the MLSoC Modalix SoM are available now through Enclustra’s exclusive Early Access Program. Customers can order today.

www.enclustra.com

This series is aimed at the intelligent edge, delivering generational gains in compute, connectivity, integration and security while complementing the company’s proven Series 2 platform. Device makers can continue to build on Series 2’s breadth and maturity for ultra‑low‑power endpoints, and adopt Series 3 for more demanding and feature‑rich designs — without changing ecosystems, tools, or support models. With SiMG301 among the first in the Alliance’s Matter Compliant Platform Certification program, teams can deliver feature‑rich, Matter‑certified products faster with pre‑tested core functionality and a clearer certification path.

“SiMG301 and SiBG301 bring Series 3’s compute and integration with the world’s first PSA Level 4 security, giving customers a stronger foundation for long‑lived, secure IoT,” said Ross Sabolcik, Senior Vice President of IoT Products at Silicon Labs.

Built on an advanced 22 nm process, Series 3 introduces a multi‑core architecture that separates application, wireless, and security workloads, providing headroom for growing protocol stacks and emerging compute-intensive use cases at the edge. The SixG301 family consists of:

• SiMG301 (Multiprotocol): Concurrent Zigbee, Bluetooth LE, and Matter over Thread; ideal for smart lighting, and other Matter-focused switches, sensors, and controllers. An integrated LED pre‑driver reduces external components, BOM cost, and board space in line‑powered designs.
• SiBG301 (Bluetooth‑Optimized): Tailored for Bluetooth LE applications that benefit from Series 3 compute and security, with an easy migration path from Series 2 Bluetooth designs.

Both devices offer developers generous Flash/RAM headroom with up to 4 MB Flash and 512 kB RAM. They both include Silicon Labs’ PIXELRZ single wire communication interface for LED controller ICs as well as a LED pre-driver that enables low level and consistent dimming, which together simplify designs, reduce costs, and provide efficient power for smart home lighting, smart building lighting, and other lighting applications.

The SiMG301 is among the first devices included in the Connectivity Standards Alliance’s new Matter Compliant Platform Certification program. A Matter Compliant Platform is a tested combination of SDK and designated hardware that has been certified by the Alliance for core Matter functionality.

By building on a certified platform, device makers can inherit pre‑tested commissioning, networking, and message security, significantly reducing the number of tests required for end‑product certification. Teams can also take advantage of the Alliance’s Fast Track and Rapid Recertification programs when the underlying platform remains unchanged, shortening development cycles and lowering costs. Products built this way are referred to as Derived Matter Products (DMPs).

Security is foundational to Series 3. Series 3 Secure Vault, debuting with the SixG301 family, has achieved the world’s first PSA Level 4 certification, the highest level recognized by PSA Certified and addresses advanced physical attacks.

This certification validates Silicon Labs SoCs equipped with Series 3 Secure Vault, like the SiMG301 and SiBG301, for resilience against laser fault injection, side-channel analysis, micro-probing, and voltage manipulation. This raises the bar for edge protection and supports alignment with tightening global regulations. The certification followed independent lab evaluation.

Built on Silicon Labs’ Series 2 security legacy, Series 3 Secure Vault includes a hardened root of trust, lifecycle controls, and secure OTA update support for products expected to live in the field for years. Silicon Labs’ Secure Vault’s features help developers reach compliance with emerging regulations including the EU’s RED and CRA and the U.S. Cyber Trust Mark, among others.

The devices, the first in the SixG301 family, are now shipping from Silicon Labs and authorized distribution partners worldwide.

www.silabs.com

“Chiplet integration is reshaping how the industry thinks about performance, scaleability and time to market,” said Robin Davis, VP of Strategic Engagements & Applications at Deca. “Our partnership with SST empowers customers to develop a chiplet solution that combines different chips, process nodes, sizes and even die from multiple foundries delivering more efficient and cost-effective products.”

Chiplet technology offers significant advantages in semiconductor design and manufacturing by enabling a more-than-Moore approach. Designers can go beyond traditional scaling to deliver enhanced functionality and performance and get products to market faster. Chiplets allow the reuse of existing IP and can facilitate the mixing of advanced process nodes with less expensive legacy geometries. By utilizing the most appropriate die technology for a particular function, chiplets provide a versatile, efficient and economical pathway for advanced semiconductor innovation.

“As our customers push the boundaries of Moore’s Law, they are expressing greater interest in chiplet-based solutions,” said Mark Reiten, Vice President of Microchip’s licensing business unit. “This partnership aims to deliver a comprehensive package of IP, simulation tools and advanced assembly and engineering services necessary for successful chiplet development and productization.”

This collaboration combines Deca’s M-Series fan-out and Adaptive Patterning technologies with SST’s industry-leading SuperFlash embedded flash technology. The companies are applying their system-level integration expertise to deliver a bundled offering that empowers customers to design, verify and commercialize NVM chiplets. By enabling greater architectural flexibility, the solution offers both technical and commercial advantages over traditional monolithic integration.

The collaborative solution provides a modular, memory-centric foundation for advanced multi-die architectures by combining the strengths of both companies. The chiplet package leverages SST’s SuperFlash technology, along with the interface logic and physical design elements required to function as a self-contained chiplet. This is paired with Adaptive Patterning-based redistribution layer (RDL) design rules, simulation flows, test strategies and manufacturing paths through Deca’s ecosystem of qualified partners.

Deca and SST will jointly support customers from early design through qualification and prototype manufacturing. By streamlining integration and accelerating design cycles, the companies aim to enable broader adoption of heterogeneous integration, engaging with customers globally to bring chiplet solutions to market.

SST website  Deca website

With industry’s first 245.76TB NVMe SSD in a 2.5-inch and enterprise and datacenter standard form factor, KIOXIA’s LC9 series drives are well-suited to generative AI and enterprise applications.

“We recognise KIOXIA for its BiCS FLASH 3D flash memory and KIOXIA LC9 Series SSD. This solution enabled by their CMOS directly bonded to array (CBA) technology and the innovation of a 32-die stacked architecture in a package deliver the capacity, power and density required for transformational SSDs. Creating the highest capacity PCIe 5.0 enterprise SSD is a remarkable achievement,” said Jay Kramer, Chair of the Awards Program and President of Network Storage Advisors. “

The combination of advanced memory architecture and CBA technology enables 8TB in a small 154 BGA package – also an industry first. This milestone was made possible with advancements in KIOXIA’s high-precision wafer processing, material design, and wire bonding technologies.

KIOXIA LC9 Series SSDs are now sampling to customers.

www.kioxia.com

The new BSM technology provides a better solution to traditional sputtering and plating processes, addressing the reliability, warpage, and increasing thermal management challenges in hybrid bonding, wafer and Panel Level Packaging (PLP) metallization.

As AI chips and high-performance computing devices continue to push the limits of processing power, thermal density has risen significantly, making efficient heat dissipation more critical than ever. Reliable bonding between semiconductor packages and Thermal Interface Materials (TIM) is essential for effective heat transfer. However, conventional BSM methods—such as sputtering and plating—pose challenges related to cost, equipment requirements, scaling at larger panels, and environmental impact.

By leveraging Merck KGaA, Darmstadt, Germany’s expertise in semiconductor coating processes and Electroninks’s Metal-Organic Decomposition (MOD) Ink technology, this collaboration aims to redefine the standards for BSM in advanced semiconductor packaging.

Merck KGaA, Darmstadt, Germany and Electroninks remain committed to advancing their strategy and commercial offerings in advanced packaging. With the commercialization of this pioneering BSM technology, which is now underway at customer sites globally,  they aim to contribute to the advancement of high-efficiency, more sustainable semiconductor packaging solutions on silicon wafer, as well as panel level processing where limited solutions exist today.

The companies plan to develop and market this technology together to customers in the near future, with on-site technical support in the US and APAC.

Find out more at www.electroninks.com

“The traction inverter is at the heart of every electrified drivetrain, and Onsemi’s EliteSiC solution plays a vital role in achieving the efficiency and performance targets that our customer demands,” said Christopher Breitsameter, Head of Business Division Controls at Schaeffler.

EliteSiC technology provides significantly lower conduction losses and superior short-circuit robustness, enabling a compact, thermally-efficient inverter design that enhances overall system performance. This silicon carbide-based solution offers the lowest on-state resistance to provide highest peak power compared to other SiC solutions in its class. These benefits allow Schaeffler to deliver an innovative traction inverter system that achieves measurable benefits to the end customer, including longer driving range, enabled by higher energy conversion efficiency, enhanced reliability and for consistent operation with lower maintenance, among others.

Energy efficiency and performance are crucial parameters in automotive design today, so the industry is focusing on more advanced hybrid architectures.. Traditionally here insulated-gate bipolar transistors (IGBTs) dominated, but silicon carbide’s beneficial parameters are helping with make the transition.

“Our industry-leading silicon carbide semiconductor technology delivers unmatched efficiency, thermal performance, and power density—key enablers for next-generation electric powertrain systems not only for battery electric vehicles, but also for plug-in Hybrid platforms,” said Simon Keeton, Group President, Power Solutions Group, Onsemi.

This new milestone builds on the existing long-term collaboration between Onsemi and Schaeffler (formerly Vitesco Technologies), extending the companies’ multi-year collaboration and reinforcing their shared commitment to delivering high-efficiency electric mobility solutions.

The new SOP Advance(E) package marks a substantial improvement over Toshiba’s existing SOP Advance(N) package, reducing package resistance by approximately 65% and thermal resistance by approximately 15%. These package enhancements directly translate into superior device performance. The 80V TPM1R908QM exhibits a reduction in drain-source on-resistance (RDS(ON)) of approximately 21% and channel-case thermal resistance (Rth(ch-c)) of approximately 15% when compared to Toshiba’s existing product, the TPH2R408QM, of same voltage rating. Similarly, the 150V TPM7R10CQ5 achieves approximately 21% lower RDS(ON) and approximately 15% lower Rth(ch-ch) than Toshiba’s existing TPH9R00CQ5, also at the same voltage. The TPM7R10CQ5 is equipped with a high speed body diode for increased efficiency in synchronous rectification.

The reductions in on-resistance and suppressed temperature rise due to improved thermal resistance contribute to a lower overall on-resistance, even considering positive temperature characteristics. This combination ultimately achieves lower loss and higher efficiency in critical applications such as switched-mode power supplies for industrial equipment, including those powering data centres and communication base stations.

The TPM1R908QM features a drain-source voltage (VDSS) of 80V, a drain current (ID) of 238A (Tc=25°C), and a maximum RDS(ON) of 1.9mΩ (VGS=10V). The TPM7R10CQ5 offers a VDSS of 150V, an ID of 120A (Tc=25°C), and a maximum RDS(ON) of 7.1mΩ (VGS=10V). Both products have a channel temperature (Tch) of 175°C and a maximum Rth(ch-c) of 0.6°C/W (Tc=25°C). The SOP Advance(E) package typically measures 4.9mm × 6.1mm.

To further support circuit design for switched-mode power supplies, Toshiba also provides a G0 SPICE model for quick circuit function verification, alongside highly accurate G2 SPICE models that precisely reproduce transient characteristics.

Please follow the links for more information on the TPM1R908QM and TPM7R10CQ5.